Post Test

The POST Test

Each time the computer boots up the computer must past the POST.

The following is the procedure of the POST:

The first step of POST is the testing of the Power Supply to ensure that it is turned on and that it releases its reset signal.

CPU must exit the reset status mode and thereafter be able to execute instructions.

BIOS must be have readable.

BIOS checksum must be valid, meaning that it must be readable.

CMOS be accessible for reading.

CMOS checksum must be valid, meaning that it must be readable.

CPU must be able to read all forms of memory such as the memory controller, memory bus, and memory module.

The first 64KB of memory must be operational and have the capability to be read and written to and from, and capable of containing the POST code.

I/O bus / controller must be accessible.

10.

I/O bus must be able to write / read from the video subsystem and be able to read all video RAM..

If the computer does not pass any of the above tests your computer will receive an irregular POST code and beep codes.

Beep Codes
1 short	DRAM refresh failure
2 short	Parity circuit failure
3 short	Base 64K RAM failure
4 short	System timer failure
5 short	CPU Process failure
6 short	Keyboard controller Gate A20 error
7 short	Virtual mode exception error
8 short	Display memory Read/Write test failure - Video Memory
9 short	ROM BIOS checksum failure
10 short	CMOS shutdown Read/Write error - CMOS Register
11 short	Cache Memory error - Cache Test
1 long, 3 short	Conventional/Extended memory failure - Memory Test
1 long, 8 short	Display/Retrace test failed - Display Test

The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS:

Checkpoint

Description

Before D1

Early chipset initialization is done. Early super I/O initialization is done including RTC and keyboard controller. NMI is disabled.

Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS.

Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum.

Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat mode is enabled.

If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled.

Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.

Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM.

Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information.

Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.

The Runtime module is uncompressed into memory. CPUID information is stored in memory.

Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM.

Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information.